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Component-Level ESD Rating

Views: 666 Update date: Jun 26,2018

The ESD protection design for an IC package is known to be critical for safe production and handling. It is commonly understood and accepted that this protection design is expected to meet or exceed the required ESD specification when these ICs are handled in an ESD-safe area, also known as ESD Protected Area (EPA) [1]. The ESD protection strategy for ICs involves discharging of the ESD events that might occur on any pin of the package that is exposed to its environment. The component-level ESD protection should consider the two basic ESD models defined for ICs: Human Body Model (HBM) and Charged Device Model (CDM). The ESD protection circuitry within MSP430™ ICs is designed based on device technology, IC pin functionalities for different applications, power pins, and so on. The protection elements are first characterized and analyzed for effectiveness using test chips. Simulations and automated checks are used, where appropriate, to ensure effectiveness of the protection circuitry and check for its compatibility with the pin it is designed to protect. Typical MSP430 devices are tested and qualified to the following industry-standard ESD ratings.


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